1. Field of the Invention
The present invention refers to capacitors and particularly to integrated capacitors with silicon and polysilicon electrodes, respectively.
2. Description of Prior Art
Nowadays, integrated circuits are used in many applications and apparatuses, such as for wireless communication. In order to satisfy the high requirements, which are demanded nowadays with regard to a behavior of such apparatuses, the devices included therein must have a high quality.
The intermodulation factor and the harmonic distortion factor (klirr-factor) represent important parameters for the usage of an analogue circuit in a wireless communication apparatus. An integrated capacitor, which is, for example, used in such an analogue circuit for a wireless communication apparatus, should therefore have a very low dependency of the capacity on the applied voltage U to obtain the above-mentioned requirements of a high quality analogue circuit.
The capacitance curve C(U) is mainly determined by charge carrier concentrations of the two capacitor electrodes, wherein the charge carrier concentrations should be as high as possible. If, for example, an upper electrode is formed of a lightly n-doped semiconductor layer, applying positive voltages to this electrode can lead to a strong depletion of charge carriers in it. Since the extension of the formed depletion zone depends on the applied voltage, a voltage dependency of the capacity results, which leads to an asymmetrical capacitance curve C(U) with a dependency on the applied voltage.
These adverse effects can be avoided by using electrodes made of a highly doped semiconductor material, or preferably made of metal.
Further, the capacitor should have a high area capacity to keep the area consumption on a chip low, wherein variations of the area capacity occurring in the production of a capacitor should be low.
Typically, an integrated capacitor is produced on a chip together with active and passive devices. In a production process, a method is desirable where an integrated capacitor can be integrated into an existing integrated overall process with as little additional steps as possible. Thereby, the number of process steps is of special significance, since additional process steps always open up additional potential sources for generating additional waste in mass production. Therefore, it is to be demanded for any integrated overall process that for the production of different devices, such as a capacitor and an active device, as many production steps as possible are shared. With the increasing miniaturization of devices on a chip, the number of phototechnique steps is of special significance, since a slight misalignment in a phototechnique method makes the device to be produced inoperable. Especially, any additional phototechnique leads to a significant raise of production costs.
It is known that due to the above-mentioned requirement of a small number of additional steps, the electrodes of an integrated capacitor are formed by polysilicon layers, which are used in other areas of the chip for generating structures of other devices, wherein a phototechnique necessary for structuring the other devices is used for structuring the capacitor electrodes. In a known method, for example, an upper electrode of an integrated condensator is formed by structuring a deposited polysilicon layer, wherein the polysilicon layer is further used for forming the gates of the CMOS transistors.
However, the above-explained generation of the electrode has the disadvantage that the overall process predetermines the dopant concentration of the polysilicon layer. The typically used dopant concentrations of deposited layers used in active devices are not sufficient to obtain a voltage dependency of the characteristic curve C(U) of the capacitor, which is sufficient for a high quality behavior of the capacitor.
FIG. 1 shows a cross-section of a known integrated capacitor, wherein the doping of the capacitor electrodes is determined by the source/drain doping of the CMOS (NMOS) transistors. According to FIG. 1, a highly conductive area 112 is formed in a silicon substrate 110 as a first electrode of the capacitor. The highly conductive area 112 is doped with phosphor as dopant to a dopant concentration of 6×1015 cm−2 and electrically isolated from further areas of the substrate by an STI trench 114 (STI=shallow trench isolation). A first dielectric layer 116 of SiO2 and a dielectric layer 118 of Si3N4 are formed on the highly conductive area 112. According to FIG. 1, the first dielectric layer of SiO2 has a thickness of 4.6 nm, while the second dielectric layer of Si3N4 has a thickness of 12 nm. A conductive polysilicon layer 120 is arranged on the second dielectric layer 118 as a second electrode, which is further used in an area, not shown in FIG. 1, for forming an active device. The polysilicon layer 120 has a thickness of 250 nm and is doped by means of arsenic doping to a doping concentration of 5×1015 cm−2. Further layers 122 and 124, which are used for contacting the second electrode, are applied over the polysilicon layer 120.
Since the doping of the capacitor electrodes of the capacitor shown in FIG. 1 is predetermined by the doping steps in a CMOS transistor process, their doping can not be selected independently, so that with the existing dopant concentrations the curve of a capacitance across an applied voltage shows an unfavorable curve due to a depletion of charge carriers in polysilicon, as will be explained below.
FIG. 2 shows a diagram of a measured curve of the capacitor of FIG. 1 having a specific capacitance of C=3 fF/μm2. In FIG. 2, an x-axis represents an applied voltage in Volt, while an y-axis represents a capacitance in nF.
As can be seen, the capacitance curve of the known capacitor of FIG. 1 is mainly constant in an area of +5 Volt to +3 Volt of a voltage applied between the second electrode of polysilicon and the first electrode, wherein the capacitance value is about 2.54 nF. With decreasing voltage at the second electrode of polysilicon, the capacitor curve shows in an area of +3 Volt to about −1 Volt a non-linear reduction of capacitance, which turns into a linear reduction with increasingly applied negative voltage at about −1 Volt, wherein the capacitance value is reduced from about 2.51 nF at −1 Volt to about 2.43 nF at −5 Volt. In this area, i.e. when the upper electrode of polysilicon is positive with respect to the lower electrode, a strong space-charge region is formed in polysilicon, whose size increases with increasingly applied negative voltage.
The characteristic curve of the capacitance curve shown in FIG. 2 is therefore highly asymmetrical and formed constant only in a small voltage area, which is why the capacitor of FIG. 1 is not suitable for the realization of a high-quality capacitor where a low voltage dependency of the capacitance is required. A known possibility to improve the voltage dependency caused by a strong depletion of the charge carriers in a polysilicon is to increase the dopant concentration of the polysilicon of the polysilicon layer 120 afterwards.
It is known that such an increase of the active charge carriers in the polysilicon layer 120 can be achieved by optimizing the temperature budget, whereby a small improvement of the capacitance curve can be achieved. However, a change of the temperature budget can only be carried out in a very tight area, since such a change has adverse influences on the functionality of the CMOS transistors generated in parallel to the capacitor.
Since the doping of the polysilicon layer 120 in the above-described integrated capacitor is not independent from the overall process and is performed more specifically by an implantation that at the same time performs a doping of the source/drain areas of the CMOS (NMOS) transistors, the doping of the polysilicon layer 120 in the above-described capacitor cannot be chosen too high, since a doping of the source/drain areas, which is too high, would lead to a breakthrough of the NMOS transistors.
It is known that improvements in the voltage dependency can be achieved by a post-doping of the arranged polysilicon layers. This can be performed, for example, by a post-ion implantation, which preferably comprises a phosphor implantation with n-conducting electrodes. However, the post-doping has the disadvantage that additional method steps, especially additional phototechnique steps, are necessary to carry out the post-implantation. As has been mentioned above, any additional phototechnique raises the costs of the overall process immensely.
Further, it is known to provide a storage capacitor and deep trench capacitor, respectively, as an integrated capacitor on the chip to obtain a favorable capacitance curve C(U). However, providing a storage capacitor has the disadvantage that for generating it a complex processing with additional process steps is required, which comprises generating the deep trench and a subsequent filling. These complex process steps again have an adverse effect on the waste in mass production. Further, a specific area capacity in a storage capacitor is only badly reproducible due to its complex arrangement in a trench, as compared to a prior art planar capacitor.
It is another known approach for generating an integrated capacitor with favorable capacitance curve to form the electrodes of the capacitors as metallic layers. In such a capacitor with metal electrodes, referred to as MIM capacitor, a very low voltage dependency of the capacitance curve results due to the high conductivity of the electrodes. However, the MIM capacitors have the disadvantage that the dielectric disposed between the metal electrodes has to be compatible with them, i.e. the deposition of the dielectrics can only be performed up to a temperature agreeable with the metal electrodes. The known dielectrics that fulfill this requirement have, however, a dielectric constant, which is lower than the one of known dielectrics that can be used for polysilicon layers. Consequently, the area capacity of a MIM capacitor is reduced in comparison to other types of integrated capacitors.